GigaDevice Semiconductor GD32VF103 - Table 13.2. Min;Max Timeout Value at 54 Mhz; Figure 13.3. Window Watchdog Timing Diagram

GD32VF103 User Manual
210
Figure 13.3. Window watchdog timing diagram
Write WWDG_CTL when CTN>WIN
cause a reset
CNT[6]=0 cause a reset
0x7F
Start
CNT[6:0]
0x3F
WIN
Write CNT
Start
Calculate the WWDGT timeout by using the formula below.
t
WWDGT
=t
PCLK1
×4096 ×2
PSC
×
󰇛
CNT
󰇟
5:0
󰇠
+1
󰇜
(ms󰇜 (13-1)
where:
t
WWDGT
: WWDGT timeout
t
PCLK1
: APB1 clock period measured in ms
Refer to the table below for the minimum and maximum values of the t
WWDGT
.
Table 13.2. Min/max timeout value at 54 MHz (f
PCLK1
)
Prescaler divider
PSC[1:0]
Min timeout value
CNT[6:0] =0x40
Max timeout value
CNT[6:0]=0x7F
1/1
00
75.8 μs
4.85ms
1/2
01
151.7 μs
9.7 ms
1/4
10
303.4 μs
19.4 ms
1/8
11
606.8 μs
38.8 ms
If the WWDGT_HOLD bit in DBG module is cleared, the WWDGT continues to work even the
RISC-V core halted (Debug mode). While the WWDGT_HOLD bit is set, the WWDGT stops
in Debug mode.