GigaDevice Semiconductor GD32VF103 - Transfer Status Register 1 (I2 C_STAT1)

GD32VF103 User Manual
377
1: STOP condition detected in slave mode
3
ADD10SEND
Header of 10-bit address is sent in master mode
This bit is set by hardware and cleared by reading I2C_STAT0 and writing
I2C_DATA.
0: No header of 10-bit address sent in master mode
1: Header of 10-bit address is sent in master mode
2
BTC
Byte transmission completed.
If a byte is already received in shift register but I2C_DATA is still full in receiving
mode or a byte is already sent out from shift register but I2C_DATA is still empty in
transmitting mode, the BTC flag is asserted if SCL stretching enabled.
This bit is set by hardware.
This bit can be cleared by 3 ways as follow:
Software clearing: read I2C_STAT0 followed by reading or writing I2C_DATA.
Hardware clearing: send the STOP condition or START condition.
Bit 0 (I2CEN bit) of the I2C_CTL0 is reset.
0: BTC not asserted
1: BTC asserted
1
ADDSEND
Address is sent in master mode or received and matches in slave mode.
This bit is set by hardware and cleared by reading I2C_STAT0 and reading
I2C_STAT1.
0: No address sent or received
1: Address sent out in master mode or a matched address is received in salve mode
0
SBSEND
START condition sent out in master mode
This bit is set by hardware and cleared by reading I2C_STAT0 and writing
I2C_DATA
0: No START condition sent
1: START condition sent
17.4.7. Transfer status register 1 (I2C_STAT1)
Address offset: 0x18
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PECV[7:0]
DUMODF
HSTSMB
DEFSMB
RXGC
Reserved
TR
I2CBSY
MASTER
r
r
r
r
r
r
r
r
Bits
Fields
Descriptions
15:8
PECV[7:0]
Packet Error Checking Value that calculated by hardware when PEC is enabled.