GigaDevice Semiconductor GD32VF103 - Page 376

GD32VF103 User Manual
376
ACKEN bit.
11
OUERR
Over-run or under-run situation occurs in slave mode, when SCL stretching is
disabled. In slave receiving mode, if the last byte in I2C_DATA is not read out while
the following byte is already received, over-run occurs. In slave transmitting mode,
if the current byte is already sent out, while the I2C_DATA is still empty, under-run
occurs.
This bit is set by hardware and cleared by writing 0.
0: No over-run or under-run occurs
1: Over-run or under-run occurs
10
AERR
Acknowledge Error
This bit is set by hardware and cleared by writing 0.
0: No Acknowledge Error
1: Acknowledge Error
9
LOSTARB
Arbitration Lost in master mode
This bit is set by hardware and cleared by writing 0.
0: No Arbitration Lost
1: Arbitration Lost occurs and the I2C block changes back to slave mode.
8
BERR
A bus error occurs indication an unexpected START or STOP condition on I2C bus
This bit is set by hardware and cleared by writing 0.
0: No bus error
1: A bus error detected
7
TBE
I2C_DATA is Empty during transmitting
This bit is set by hardware after it moves a byte from I2C_DATA to shift register and
cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are
empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
0: I2C_DATA is not empty
1: I2C_DATA is empty, software can write
6
RBNE
I2C_DATA is not Empty during receiving
This bit is set by hardware after it moves a byte from shift register to I2C_DATA and
cleared by reading I2C_DATA. If both BTC and RBNE are asserted, reading
I2C_DATA won’t clear RBNE because the shift register’s byte is moved to
I2C_DATA immediately.
0: I2C_DATA is empty
1: I2C_DATA is not empty, software can read
5
Reserved
Must be kept the reset value.
4
STPDET
STOP condition detected in slave mode
This bit is set by hardware and cleared by reading I2C_STAT0 and then writing
I2C_CTL0
0: STOP condition not detected in slave mode