GigaDevice Semiconductor GD32VF103 - Table 15-1. Timers (Timerx) Are Devided into Three Sorts; 15 Timer(Timerx)

GD32VF103 User Manual
222
15. Timer(TIMERx)
Table 15-1. Timers (TIMERx) are devided into three sorts
TIMER
TIMER0
TIMER1/2/3/4
TIMER5/6
TYPE
Advanced
General-L0
Basic
Prescaler
16-bit
16-bit
16-bit
Counter
16-bit
16-bit
16-bit
Count mode
UP,DOWN,
Center-aligned
UP,DOWN,
Center-aligned
UP ONLY
Repetition
●
×
×
CH Capture/
Compare
4
4
0
Complementary
& Dead-time
●
×
×
Break
●
×
×
Single Pulse
●
●
●
Quadrature
Decoder
●
●
×
Slave Controller
●
●
×
Inter connection
●
(1)
●
(2)
TRGO TO DAC
DMA
●
●
●
(3)
Debug Mode
●
●
●
(1)
TIMER0
ITI0: TIMER4_TRGO
ITI1: TIMER1_TRGO
ITI2: TIMER2_TRGO
ITI3: TIMER3_TRGO
(2)
TIMER1
ITI0: TIMER0_TRGO
ITI1: refer to note (4)
ITI2: TIMER2_TRGO
ITI3: TIMER3_TRGO
TIMER2
ITI0: TIMER0_TRGO
ITI1: TIMER1_TRGO
ITI2: TIMER4_TRGO
ITI3: TIMER3_TRGO
TIMER3
ITI0: TIMER0_TRGO
ITI1: TIMER1_TRGO
ITI2: TIMER2_TRGO
ITI3: 0
TIMER4
ITI0: TIMER1_TRGO
ITI1: TIMER2_TRGO
ITI2: TIMER3_TRGO
ITI3: 0
(3)
Only update events will generate DMA request. Note that TIMER5/6 do not have DMA configuration
registers.
(4)
The source of TIMER1 ITI1 is decided by TIMER1ITI1_REMAP in AFIO port configuration register
0 (AFIO_PCF0);