GigaDevice Semiconductor GD32VF103 - 6 Interrupt;Event Controller (EXTI); Characteristics; Function Overview; Overview

GD32VF103 User Manual
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6. Interrupt/event controller (EXTI)
6.1. Overview
RISC-V integrates the Enhancement Core-Local Interrupt Controller (ECLIC) for efficient
interrupts processing. ECLIC is designed to provide low-latency, vectored, pre-emptive
interrupts for RISC-V systems. When activated the ECLIC subsumes and replaces the
existing RISC-V local interrupt scheme (CLINT). The CLIC design has a base design that
requires minimal hardware, but supports additional extensions to provide hardware
acceleration. The goal of the ECLIC design is to provide support for a variety of software ABI
and interrupt models, without complex hardware that can impact high-performance processor
implementations. It’s tightly coupled to the processer core. You can read the Technical
Reference Manual of RISC-V for more details about ECLIC.
EXTI (interrupt/event controller) contains up to 19 independent edge detectors and generates
interrupt requests or events to the processer. The EXTI has three trigger types: rising edge,
falling edge and both edges. Each edge detector in the EXTI can be configured and masked
independently.
6.2. Characteristics
 Up to 68 maskable peripheral interrupts.
 4 bits interrupt priority configuration - 16 priority levels.
 Support interrupt pre-emption and tail-chaining.
 Wake up system from power saving mode.
 Up to 19 independent edge detectors in EXTI.
 Three trigger types: rising, falling and both edges.
 Software interrupt or event trigger.
 Trigger sources configurable.
6.3. Function overview
The RISC-V processor and the Enhancement Core-Local Interrupt Controller (ECLIC)
prioritize and handle all interrupts in machine mode.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. The following tables list all interrupt
types.