GD32VF103 User Manual
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19.3.3. External device address mapping
Figure 19-2. EXMC memory banks
Bank0(4x64M)
0x6000 0000
0x6FFF FFFF
Address Banks Supported memory type
NOR/PSRAM
EXMC access space is divided into one bank. Bank0 is 4*64 Mbytes. The first bank (Bank0)
is further divided into 4 Regions, which is 64 Mbytes (only Bank0 Region0 is used).
Each bank or region has a separate chip-select control signal, which can be configured
independently.
Bank0 is used for NOR and PSRAM device access.
NOR/PSRAM address mapping
Figure 19-3. Region of bank0 address mapping reflects the address mapping of the region
of bank0. Internal AHB address lines HADDR[27:26] bits are used to select the region, but
only region0 is supported.
Figure 19-3. Region of bank0 address mapping
Region0
0x60000000
NOR/PSRAM
HADDR[27:26] Address Regions Supported memory type
00
0x63FFFFFF
HADDR[25:0] is the byte address whereas the external memory may not be byte accessed,
this will lead to address inconsistency. EXMC can adjust HADDR to accommodate the data
width of the external memory according to the following rules.
– When data bus width of the external memory is 8-bits. In this case the memory address
is byte aligned. HADDR[25:0] is connected to EXMC_A[25:0] and then the EXMC_A[25:0]
is connected to the external memory address lines.
– When data bus width of the external memory is 16-bits. In this case the memory address
is half-word aligned. HADDR byte address must be converted into half-word aligned by
connecting HADDR[25:1] with EXMC_A[24:0]. The EXMC_A[24:0] is connected to the
external memory address lines.
19.3.4. NOR/PSRAM controller
NOR/PSRAM memory controller controls bank0, which is designed to support NOR Flash,
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