GigaDevice Semiconductor GD32VF103 - Regular Sequence Register 1 (ADC_RSQ1); Regular Sequence Register 2 (ADC_RSQ2)

GD32VF103 User Manual
183
9:5
RSQ13[4:0]
refer to RSQ0[4:0] description
4:0
RSQ12[4:0]
refer to RSQ0[4:0] description
11.8.10. Regular sequence register 1 (ADC_RSQ1)
Address offset: 0x30
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
RSQ11[4:0]
RSQ10[4:0]
RSQ9[4:1]
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSQ9[0]
RSQ8[4:0]
RSQ7[4:0]
RSQ6[4:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value
29:25
RSQ11[4:0]
refer to RSQ0[4:0] description
24:20
RSQ10[4:0]
refer to RSQ0[4:0] description
19:15
RSQ9[4:0]
refer to RSQ0[4:0] description
14:10
RSQ8[4:0]
refer to RSQ0[4:0] description
9:5
RSQ7[4:0]
refer to RSQ0[4:0] description
4:0
RSQ6[4:0]
refer to RSQ0[4:0] description
11.8.11. Regular sequence register 2 (ADC_RSQ2)
Address offset: 0x34
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
RSQ5[4:0]
RSQ4[4:0]
RSQ3[4:1]
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSQ3[0]
RSQ2[4:0]
RSQ1[4:0]
RSQ0[4:0]
rw
rw
rw
rw
Bits
Fields
Descriptions