GigaDevice Semiconductor GD32VF103 - Control Register (FMC_CTL)

GD32VF103 User Manual
43
When erase/program on protected pages, this bit is set by hardware. The software
can clear it by writing 1.
3
Reserved
Must be kept at reset value.
2
PGERR
Program error flag bit
When program to the flash while it is not 0xFFFF, this bit is set by hardware. The
software can clear it by writing 1.
1
Reserved
Must be kept at reset value.
0
BUSY
The flash busy bit
When the operation is in progress, this bit is set to 1. When the operation is end or
an error is generated, this bit is cleared.
2.4.5. Control register (FMC_CTL)
Address offset: 0x10
Reset value: 0x0000 0080
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ENDIE
Reserved
ERRIE
OBWEN
Reserved
LK
START
OBER
OBPG
Reserved
MER
PER
PG
rw
rw
rw
rs
rs
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value.
12
ENDIE
End of operation interrupt enable bit
This bit is set or cleared by software
0: no interrupt generated by hardware.
1: end of operation interrupt enable
11
Reserved
Must be kept at reset value.
10
ERRIE
Error interrupt enable bit
This bit is set or cleared by software
0: no interrupt generated by hardware.
1: error interrupt enable
9
OBWEN
Option byte erase/program enable bit
This bit is set by hardware when right sequence written to FMC_OBKEY register.
This bit can be cleared by software.