GigaDevice Semiconductor GD32VF103 - Port Input Status Register (Gpiox_Istat, X=A

GD32VF103 User Manual
116
refer to CTL0[1:0]description
17:16
MD12[1:0]
Port 12 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
15:14
CTL11[1:0]
Port 11 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
13:12
MD11[1:0]
Port 11 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
11:10
CTL10[1:0]
Port 10 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
9:8
MD10[1:0]
Port 10 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
7:6
CTL9[1:0]
Port 9 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
5:4
MD9[1:0]
Port 9 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
3:2
CTL8[1:0]
Port 8 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
1:0
MD8[1:0]
Port 8 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
7.5.3. Port input status register (GPIOx_ISTAT, x=A..E)
Address offset: 0x08
Reset value: 0x0000 XXXX
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0