GigaDevice Semiconductor GD32VF103 - System and Memory Architecture; RISC-V CPU; System Architecture; Memory Map

GD32VF103 User Manual
2
Table of Contents
Table of Contents ............................................................................................................... 2
List of Figures ................................................................................................................... 14
List of Tables ..................................................................................................................... 20
1. System and memory architecture ........................................................................... 22
1.1. RISC-V CPU ......................................................................................................................... 22
1.2. System architecture ............................................................................................................ 22
1.3. Memory map ..................................................................................................................... 24
1.3.1. On-chip SRAM memory ................................................................................................................... 28
1.3.2. On-chip flash memory overview ..................................................................................................... 28
1.4. Boot configuration ............................................................................................................. 29
1.5. Device electronic signature ................................................................................................. 29
1.5.1. Memory density information ............................................................................................................ 30
1.5.2. Unique device ID (96 bits) ............................................................................................................... 30
2. Flash memory controller (FMC) ............................................................................... 32
2.1. Overview ........................................................................................................................... 32
2.2. Characteristics .................................................................................................................... 32
2.3. Function overview .............................................................................................................. 32
2.3.1. Flash memory architecture .............................................................................................................. 32
2.3.2. Read operations ................................................................................................................................ 33
2.3.3. Unlock the FMC_CTL registers ...................................................................................................... 33
2.3.4. Page erase ........................................................................................................................................ 33
2.3.5. Mass erase ........................................................................................................................................ 34
2.3.6. Main flash programming .................................................................................................................. 35
2.3.7. Option bytes Erase ........................................................................................................................... 37
2.3.8. Option bytes modify .......................................................................................................................... 38
2.3.9. Option bytes description .................................................................................................................. 38
2.3.10. Page erase/program protection ...................................................................................................... 39
2.3.11. Security protection ............................................................................................................................ 40
2.4. Register definition .............................................................................................................. 41
2.4.1. Wait state register (FMC_WS) ........................................................................................................ 41
2.4.2. Unlock key register (FMC_KEY)..................................................................................................... 41
2.4.3. Option byte unlock key register (FMC_OBKEY) .......................................................................... 42
2.4.4. Status register (FMC_STAT) ........................................................................................................... 42
2.4.5. Control register (FMC_CTL) ............................................................................................................ 43
2.4.6. Address register (FMC_ADDR) ...................................................................................................... 44