GigaDevice Semiconductor GD32VF103 - Table 19-1. nor Flash Interface Signals Description; Table 19-3. EXMC Bank 0 Supports All Transactions; Table 19-2. PSRAM Muxed Signal Description

GD32VF103 User Manual
419
PSRAM, SRAM, ROM and honeycomb RAM external memory. EXMC has 1 independent
chip-select signals for 1 sub-bank within bank0, named NE[0]. Other signals for NOR/PSRAM
access are shared. Each sub-bank has its own set of configuration register.
Note:
In asynchronous mode, all output signals of controller will change on the rise edge of internal
AHB bus clock (HCLK).
NOR/PSRAM memory device interface description
Table 19-1. NOR Flash interface signals description
EXMC Pin
Direction
Mode
Functional description
Muxed EXMC_A[25:16]
Output
Async
Address bus signal
EXMC_D[15:0]
Input/output
Async
Address/Data bus
EXMC_NE[x]
Output
Async
Chip selection, x=0
EXMC_NOE
Output
Async
Read enable
EXMC_NWE
Output
Async
Write enable
EXMC_NWAIT
Input
Async
Wait input signal
EXMC_NL(NADV)
Output
Async
Address valid
Table 19-2. PSRAM muxed signal description
EXMC Pin
Direction
Mode
Functional description
EXMC_A[25:16]
Output
Async
Address Bus
EXMC_D[15:0]
Input/output
Async
Data Bus
EXMC_NE[x]
Output
Async
Chip selection, x=0
EXMC_NOE
Output
Async
Read enable
EXMC_NWE
Output
Async
Write enable
EXMC_NWAIT
Input
Async
Wait input signal
EXMC_NL(NADV)
Output
Async
Latch enable (address
valid enable, NADV)
EXMC_NBL[1]
Output
Async
Upper byte enable
EXMC_NBL[0]
Output
Async
Lower byte enable
Supported memory access mode
Table below shows an example of the supported devices type, access modes and
transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.
Table 19-3. EXMC bank 0 supports all transactions
Memory
Access Mode
R/W
AHB
Transaction
Size
Memory
Transaction
Size
Comments
NOR Flash
Async
R
8
16
Async
R
16
16
Async
W
16
16