GigaDevice Semiconductor GD32VF103 - Status Register (SPI_STAT)

GD32VF103 User Manual
409
1: NSS output is enabled. If the NSS pin is configured as output, the NSS pin is
pulled low in master mode when SPI is enabled.
If the NSS pin is configured as input, the NSS pin should be pulled high in master
mode, and this bit has no effect.
1
DMATEN
Transmit buffer DMA enable
0: Transmit buffer DMA is disabled.
1: Transmit buffer DMA is enabled, when the TBE bit in SPI_STAT is set, there will
be a DMA request on corresponding DMA channel.
0
DMAREN
Receive buffer DMA enable
0: Receive buffer DMA is disabled.
1: Receive buffer DMA is enabled, when the RBNE bit in SPI_STAT is set, there will
be a DMA request on corresponding DMA channel.
18.11.3. Status register (SPI_STAT)
Address offset: 0x08
Reset value: 0x0002
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FERR
TRANS
RXORER
R
CONFER
R
CRCERR
TXURER
R
I2SCH
TBE
RBNE
rc_w0
r
r
r
rc_w0
r
r
r
r
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
FERR
Format error
SPI TI Mode:
0: No TI mode format error
1: TI mode format error occurs
I2S Mode:
0: No I2S format error
1: I2S format error occurs
This bit is set by hardware and cleared by writing 0.
7
TRANS
Transmitting ongoing bit
0: SPI or I2S is idle.
1: SPI or I2S is currently transmitting and/or receiving a frame
This bit is set and cleared by hardware.