GigaDevice Semiconductor GD32VF103 - DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8 DH); DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12 DH)

GD32VF103 User Manual
197
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:4
DAC0_DH[11:0]
DAC0 12-bit left-aligned data
These bits specify the data that is to be converted by DAC0.
3:0
Reserved
Must be kept at reset value
12.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)
Address offset: 0x10
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC0_DH[7:0]
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value
7:0
DAC0_DH[7:0]
DAC0 8-bit right-aligned data
These bits specify the MSB 8 bits of the data that is to be converted by DAC0.
12.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC1_DH[11:0]
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value
11:0
DAC1_DH[11:0]
DAC1 12-bit right-aligned data