GigaDevice Semiconductor GD32VF103 - I2 S Control Register (SPI_I2 SCTL)

GD32VF103 User Manual
413
The hardware computes the CRC value after each transmitted bit, when the TRANS
is set, a read to this register could return an intermediate value. The different frame
formats (LF bit of the SPI_CTL0) will get different CRC values.
This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit
in RCU reset register is set.
18.11.8. I2S control register (SPI_I2SCTL)
Address offset: 0x1C
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
I2SSEL
I2SEN
I2SOPMOD[1:0]
PCMSMO
D
Reserved
I2SSTD[1:0]
CKPL
DTLEN[1:0]
CHLEN
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value.
11
I2SSEL
I2S mode selection
0: SPI mode
1: I2S mode
This bit should be configured when SPI/I2S is disabled.
10
I2SEN
I2S enable
0: I2S is disabled
1: I2S is enabled
This bit is not used in SPI mode.
9:8
I2SOPMOD[1:0]
I2S operation mode
00: Slave transmission mode
01: Slave reception mode
10: Master transmission mode
11: Master reception mode
This bit should be configured when I2S is disabled.
This bit is not used in SPI mode.
7
PCMSMOD
PCM frame synchronization mode
0: Short frame synchronization
1: Long frame synchronization
This bit has a meaning only when PCM standard is used.