GigaDevice Semiconductor GD32VF103 - Figure 9-5. DMA1 Request Mapping

GD32VF103 User Manual
140
Table 9-3. DMA0 requests for each channel
Periphera
l
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
TIMER0
●
TIMER0_CH0
TIMER0_CH1
TIMER0_CH3
TIMER0_TG
TIMER0_CM
T
TIMER0_UP
TIMER0_CH2
●
TIMER1
TIMER1_CH2
TIMER1_UP
●
●
TIMER1_CH0
●
TIMER1_CH1
TIMER1_CH3
TIMER2
●
TIMER2_CH2
TIMER2_CH3
TIMER2_UP
●
●
TIMER2_CH0
TIMER2_TG
●
TIMER3
TIMER3_CH0
●
●
TIMER3_CH1
TIMER3_CH2
●
TIMER3_UP
ADC0
ADC0
●
●
●
●
●
●
SPI/I2S
●
SPI0_RX
SPI0_TX
SPI1/I2S1_R
X
SPI1/I2S1_T
X
●
●
USART
●
USART2_TX
USART2_RX
USART0_TX
USART0_RX
USART1_RX
USART1_TX
I2C
●
●
●
I2C1_TX
I2C1_RX
I2C0_TX
I2C0_RX
Figure 9-5. DMA1 request mapping
SPI2/I2S2_RX
TIMER4_CH3
TIMER4_TG
or
or
Channel 0
MEMTOMEM0
Hardware
priority
high
low
SPI2/I2S2_TX
TIMER4_CH2
TIMER4_UP
or
or
Channel 1
MEMTOMEM2MEMTOMEM1
UART3_RX
TIMER5_UP
DAC_CH0
or
or
Channel 2
MEMTOMEM2
TIMER4_CH1
TIMER6_UP
DAC_CH1
or
or
Channel 3
MEMTOMEM4
MEMTOMEM3
UART3_TX
TIMER4_CH0
or
or
Channel 4
MEMTOMEM4