GigaDevice Semiconductor GD32VF103 - Filter Associated FIFO Register (CAN_FAFIFO); Filter Scale Configuration Register (CAN_FSCFG)

GD32VF103 User Manual
458
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27:0
FMODx
Filter mode
0: Filter x with Mask mode
1: Filter x with List mode
20.4.19. Filter scale configuration register (CAN_FSCFG)
Address offset: 0x20C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit). This register can be modified only when
FLD bit in CAN_FCTL register is set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FS27
FS26
FS25
FS24
FS23
FS22
FS21
FS20
FS19
FS18
FS17
FS16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FS15
FS14
FS13
FS12
FS11
FS10
FS9
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
FS0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27:0
FSx
Filter scale
0: Filter x with 16-bit scale
1: Filter x with 32-bit scale
20.4.20. Filter associated FIFO register (CAN_FAFIFO)
Address offset: 0x214
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit). This register can be modified only when
FLD bit in CAN_FCTL register is set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FAF27
FAF26
FAF25
FAF24
FAF23
FAF22
FAF21
FAF20
FAF19
FAF18
FAF17
FAF16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FAF15
FAF14
FAF13
FAF12
FAF11
FAF10
FAF9
FAF8
FAF7
FAF6
FAF5
FAF4
FAF3
FAF2
FAF1
FAF0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw