GigaDevice Semiconductor GD32VF103 - Register Definition; NOR;PSRAM Controller Registers

GD32VF103 User Manual
424
19.4. Register definition
EXMC base address: 0xA000 0000
19.4.1. NOR/PSRAM controller registers
SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0)
Address offset: 0x00 + 8 * x, (x = 0)
Reset value: 0x0000 30DA for region0.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ASYNC
WAIT
Reserved
NRWTEN
WREN
Reserved
NRWT
POL
Reserved
NREN
NRW[1:0]
NRTP[1:0]
NRMUX
NRBKEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15
ASYNCWAIT
Asynchronous wait
0: Disable the asynchronous wait feature
1: Enable the asynchronous wait feature
14
Reserved
Must be kept at reset value.
13
NRWTEN
NWAIT signal enable
For Flash memory access in burst mode, this bit enables/disables wait-state
insertion via the NWAIT signal:
0: Disable NWAIT signal
1: Enable NWAIT signal
12
WREN
Write enable
0: Disabled write in the bank by the EXMC, otherwise an AHB error is reported
1: Enabled write in the bank by the EXMC (default after reset)
11:10
Reserved
Must be kept at reset value.
9
NRWTPOL
NWAIT signal polarity
0: Low level is active of NWAIT
1: High level is active of NWAIT