GigaDevice Semiconductor GD32VF103 - Interrupt Flag Clear Register (DMA_INTC); Channel X Control Register (Dma_Chxctl)

GD32VF103 User Manual
143
9.5.2. Interrupt flag clear register (DMA_INTC)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
ERRIFC6
HTFIFC6
FTFIFC6
GIFC6
ERRIFC5
HTFIFC5
FTFIFC5
GIFC5
ERRIFC4
HTFIFC4
FTFIFC4
GIFC4
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERRIFC3
HTFIFC3
FTFIFC3
GIFC3
ERRIFC2
HTFIC2
FTFIFC2
GIFC2
ERRIFC1
HTFIFC1
FTFIFC1
GIFC1
ERRIFC0
HTFIFC0
FTFIFC0
GIFC0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value.
27/23/19/
15/11/7/3
ERRIFCx
Clear bit for error flag of channel x (x=0…6)
0: No effect
1: Clear error flag
26/22/18/
14/10/6/2
HTFIFCx
Clear bit for half transfer finish flag of channel x (x=0…6)
0: No effect
1: Clear half transfer finish flag
25/21/17/
13/9/5/1
FTFIFCx
Clear bit for full transfer finish flag of channel x (x=0…6)
0: No effect
1: Clear full transfer finish flag
24/20/16/
12/8/4/0
GIFCx
Clear global interrupt flag of channel x (x=0…6)
0: No effect
1: Clear GIFx, ERRIFx, HTFIFx and FTFIFx bits in the DMA_INTF register
9.5.3. Channel x control register (DMA_CHxCTL)
x = 0...6, where x is a channel number
Address offset: 0x08 + 0x14 × x
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
M2M
PRIO[1:0]
MWIDTH[1:0]
PWIDTH[1:0]
MNAGA
PNAGA
CMEN
DIR
ERRIE
HTFIE
FTFIE
CHEN