GigaDevice Semiconductor GD32VF103 - Regular Sequence Register 0 (ADC_RSQ0); Watchdog Low Threshold Register (ADC_WDLT)

GD32VF103 User Manual
182
These bits define the high threshold for the analog watchdog.
11.8.8. Watchdog low threshold register (ADC_WDLT)
Address offset: 0x28
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WDLT[11:0]
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value
11:0
WDLT[11:0]
Analog watchdog low threshold
These bits define the low threshold for the analog watchdog.
11.8.9. Regular sequence register 0 (ADC_RSQ0)
Address offset: 0x2C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
RL[3:0]
RSQ15[4:1]
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSQ15[0]
RSQ14[4:0]
RSQ13[4:0]
RSQ12[4:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value
23:20
RL[3:0]
Regular channel group length.
The total number of conversion in regular group equals to RL[3:0]+1.
19:15
RSQ15[4:0]
refer to RSQ0[4:0] description
14:10
RSQ14[4:0]
refer to RSQ0[4:0] description