GigaDevice Semiconductor GD32VF103 - GPIO Pin Configuration; Figure 7.1. Basic Structure of a Standard I;O Port Bit

GD32VF103 User Manual
103
Configuration mode
CTL[1:0]
MD[1:0]
OCTL
Input
Analog
00
0
don’t care
Input floating
01
don’t care
Input pull-down
10
0
Input pull-up
10
1
General purpose
Output (GPIO)
Push-pull
00
00: Reserved
01: Speed up to 10MHz
10: Speed up to 2MHz
11: Speed up to 50MHz
0 or 1
Open-drain
01
0 or 1
Alternate Function
Output (AFIO)
Push-pull
10
don’t care
Open-drain
11
don’t care
Figure 7.1. Basic structure of a standard I/O port bit shows the basic structure of an I/O
port bit.
Figure 7.1. Basic structure of a standard I/O port bit
Vss
Output
Control
Vdd
Output
Control
Register
Input
Status
Register
Write
Read/Write
Alternate Function Output
Read
Alternate Function Input
Analog ( Input / Output )
Input driver
Output driver
I/O pin
Schmitt
trigger
Bit Operate
Registers
ESD
protection
Vdd
Vss
7.3.1. GPIO pin configuration
During or just after the reset period, the alternative functions are all inactive and the GPIO
ports are configured into the input floating mode that input disabled without Pull-Up (PU)/Pull-
Down (PD) resistors. But the JTAG/Serial-Wired Debug pins are in input PU/PD mode after
reset:
PA15: JTDI in PU mode.
PA14: JTCK in PD mode.
PA13: JTMS in PU mode.
PB4: NJTRST in PU mode.
PB3: JTDO in Floating mode.