GigaDevice Semiconductor GD32VF103 - Transfer Buffer Register (I2 C_DATA); Transfer Status Register 0 (I2 C_STAT0)

GD32VF103 User Manual
375
17.4.5. Transfer buffer register (I2C_DATA)
Address offset: 0x10
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TRB[7:0]
rw
Bits
Fields
Descriptions
15:8
Reserved
Must be kept the reset value.
7:0
TRB[7:0]
Transmission or reception data buffer
17.4.6. Transfer status register 0 (I2C_STAT0)
Address offset: 0x14
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMBALT
SMBTO
Reserved
PECERR
OUERR
AERR
LOSTAR
B
BERR
TBE
RBNE
Reserved
STPDET
ADD10S
END
BTC
ADDSEN
D
SBSEND
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
r
r
r
r
r
r
r
Bits
Fields
Descriptions
15
SMBALT
SMBus Alert status
This bit is set by hardware and cleared by writing 0.
0: SMBA pin not pulled down (device mode) or no Alert detected (host mode)
1: SMBA pin pulled down (device mode) or Alert detected (host mode)
14
SMBTO
Timeout signal in SMBus mode
This bit is set by hardware and cleared by writing 0.
0: No timeout error
1: Timeout event occurs (SCL is low for 25 ms)
13
Reserved
Must keep the reset value.
12
PECERR
PEC error when receiving data
This bit is set by hardware and cleared by writing 0.
0: Received PEC and calculated PEC match
1: Received PEC and calculated PEC don’t match, I2C will send NACK careless of