GigaDevice Semiconductor GD32VF103 - DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12 DH); DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12 DH)

GD32VF103 User Manual
199
12.4.9. DAC concurrent mode 12-bit right-aligned data holding register
(DACC_R12DH)
Address offset: 0x20
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DAC1_DH[11:0]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC0_DH[11:0]
rw
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27:16
DAC1_DH[11:0]
DAC1 12-bit right-aligned data
These bits specify the data that is to be converted by DAC1.
15:12
Reserved
Must be kept at reset value
11:0
DAC0_DH[11:0]
DAC0 12-bit right-aligned data
These bits specify the data that is to be converted by DAC0.
12.4.10. DAC concurrent mode 12-bit left-aligned data holding register
(DACC_L12DH)
Address offset: 0x24
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DAC1_DH[11:0]
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC0_DH[11:0]
Reserved
rw
Bits
Fields
Descriptions
31:20
DAC1_DH[11:0]
DAC1 12-bit left-aligned data
These bits specify the data that is to be converted by DAC1.