GigaDevice Semiconductor GD32VF103 - Page 425

GD32VF103 User Manual
425
8:7
Reserved
Must be kept at reset value.
6
NREN
NOR Flash access enable
0: Disable NOR Flash access
1: Enable NOR Flash access
5:4
NRW[1:0]
NOR region memory data bus width
00: 8 bits
01: 16 bits(default after reset)
10/11: Reserved
3:2
NRTP[1:0]
NOR region memory type
00: SRAM
01: PSRAM（CRAM）
10: NOR Flash(default after reset for region0)
11: Reserved
1
NRMUX
NOR region memory address/data multiplexing
0: Disable address/data multiplexing function
1: Enable address/data multiplexing function
0
NRBKEN
NOR region enable
0: Disable the corresponding memory bank
1: Enable the corresponding memory bank
SRAM/NOR Flash timing configuration registers (EXMC_SNTCFGx) (x=0)
Address offset: 0x04 + 8 * x, (x = 0)
Reset value: 0x0FFF FFFF
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
BUSLAT[3:0]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DSET[7:0]
AHLD[3:0]
ASET[3:0]
rw
rw
rw
Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value.
19:16
BUSLAT[3:0]
Bus latency
The bits are defined in multiplexed read mode in order to avoid bus contention,
and represent the data bus to return to a high impedance state's minimum.
0x0: Bus latency = 1 * HCLK period
0x1: Bus latency = 2 * HCLK period