GigaDevice Semiconductor GD32VF103 - Page 426

GD32VF103 User Manual
426
……
0xF: Bus latency = 16 * HCLK period
15:8
DSET[7:0]
Data setup time
This field is meaningful only in asynchronous access.
0x00: Reserved
0x01: Data setup time = 2 * HCLK period
……
0xFF: Data setup time = 256 * HCLK period
7:4
AHLD[3:0]
Address hold time
This field is used to set the time of address hold phase.
0x0: Reserved
0x1: Address hold time = 2 * HCLK
……
0xF: Address hold time = 16 * HCLK
3:0
ASET[3:0]
Address setup time
This field is used to set the time of address setup phase.
Note: meaningful only in asynchronous access of SRAM,ROM,NOR Flash
0x0: Address setup time = 1 * HCLK
……
0xF: Address setup time = 16 * HCLK