GigaDevice Semiconductor GD32VF103 - Page 3

GD32VF103 User Manual
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2.4.7. Option byte status register (FMC_OBSTAT) ................................................................................. 45
2.4.8. Erase/Program Protection register (FMC_WP) ............................................................................ 45
2.4.9. Product ID register (FMC_PID) ...................................................................................................... 46
3. Power management unit (PMU) ............................................................................... 47
3.1. Overview ........................................................................................................................... 47
3.2. Characteristics .................................................................................................................... 47
3.3. Function overview .............................................................................................................. 47
3.3.1. Battery backup domain .................................................................................................................... 48
3.3.2. V
DD
/V
DDA
power domain ................................................................................................................... 49
3.3.3. 1.2V power domain ........................................................................................................................... 51
3.3.4. Power saving modes ........................................................................................................................ 51
3.4. Register definition .............................................................................................................. 54
3.4.1. Control register (PMU_CTL) ........................................................................................................... 54
3.4.2. Control and status register (PMU_CS) .......................................................................................... 55
4. Backup registers (BKP) ............................................................................................ 57
4.1. Overview ........................................................................................................................... 57
4.2. Characteristics .................................................................................................................... 57
4.3. Function overview .............................................................................................................. 57
4.3.1. RTC clock calibration ....................................................................................................................... 57
4.3.2. Tamper detection .............................................................................................................................. 58
4.4. Register definition .............................................................................................................. 59
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) ......................................................................... 59
4.4.2. RTC signal output control register (BKP_OCTL) ......................................................................... 59
4.4.3. Tamper pin control register (BKP_TPCTL) ................................................................................... 60
4.4.4. Tamper control and status register (BKP_TPCS) ........................................................................ 60
5. Reset and clock unit (RCU) ...................................................................................... 62
5.1. Reset control unit (RCTL) .................................................................................................... 62
5.1.1. Overview ............................................................................................................................................ 62
5.1.2. Function overview ............................................................................................................................. 62
5.2. Clock control unit (CCTL) ..................................................................................................... 63
5.2.1. Overview ............................................................................................................................................ 63
5.2.2. Characteristics................................................................................................................................... 65
5.2.3. Function overview ............................................................................................................................. 65
5.3. Register definition .............................................................................................................. 69
5.3.1. Control register (RCU_CTL) ............................................................................................................ 69
5.3.2. Clock configuration register 0 (RCU_CFG0) ................................................................................ 71
5.3.3. Clock interrupt register (RCU_INT) ................................................................................................ 74
5.3.4. APB2 reset register (RCU_APB2RST) .......................................................................................... 77