GD32VF103 User Manual
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5.3.5. APB1 reset register (RCU_APB1RST) .......................................................................................... 79
5.3.6. AHB enable register (RCU_AHBEN) ............................................................................................. 82
5.3.7. APB2 enable register (RCU_APB2EN) ......................................................................................... 83
5.3.8. APB1 enable register (RCU_APB1EN) ......................................................................................... 85
5.3.9. Backup domain control register (RCU_BDCTL) .......................................................................... 87
5.3.10. Reset source/clock register (RCU_RSTSCK) .............................................................................. 88
5.3.11. AHB reset register (RCU_AHBRST) .............................................................................................. 90
5.3.12. Clock configuration register 1 (RCU_CFG1) ................................................................................ 91
5.3.13. Deep-sleep mode voltage register (RCU_DSV) .......................................................................... 93
6. Interrupt/event controller (EXTI) .............................................................................. 94
6.1. Overview ........................................................................................................................... 94
6.2. Characteristics .................................................................................................................... 94
6.3. Function overview .............................................................................................................. 94
6.4. External interrupt and event (EXTI) block diagram ............................................................... 97
6.5. External Interrupt and Event function overview .................................................................. 97
6.6. Register definition .............................................................................................................. 99
6.6.1. Interrupt enable register (EXTI_INTEN) ........................................................................................ 99
6.6.2. Event enable register (EXTI_EVEN) .............................................................................................. 99
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ..................................................................... 100
6.6.4. Falling edge trigger enable register (EXTI_FTEN) .................................................................... 100
6.6.5. Software interrupt event register (EXTI_SWIEV) ....................................................................... 101
6.6.6. Pending register (EXTI_PD) .......................................................................................................... 101
7. General-purpose and alternate-function I/Os (GPIO and AFIO) ........................ 102
7.1. Overview ......................................................................................................................... 102
7.2. Characteristics .................................................................................................................. 102
7.3. Function overview ............................................................................................................ 102
7.3.1. GPIO pin configuration ................................................................................................................... 103
7.3.2. External interrupt/event lines ........................................................................................................ 104
7.3.3. Alternate functions (AF) ................................................................................................................. 104
7.3.4. Input configuration .......................................................................................................................... 104
7.3.5. Output configuration ....................................................................................................................... 105
7.3.6. Analog configuration ....................................................................................................................... 106
7.3.7. Alternate function (AF) configuration ........................................................................................... 106
7.3.8. IO pin function selection ................................................................................................................ 107
7.3.9. GPIO locking function .................................................................................................................... 107
7.4. Remapping function I/O and debug configuration ............................................................. 108
7.4.1. Introduction ...................................................................................................................................... 108
7.4.2. Main features ................................................................................................................................... 108
7.4.3. JTAG alternate function remapping ............................................................................................. 108
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