GD32VF103 User Manual
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7.4.4. TIMER AF remapping ..................................................................................................................... 109
7.4.5. USART AF remapping .................................................................................................................... 110
7.4.6. I2C0 AF remapping ......................................................................................................................... 110
7.4.7. SPI0 AF remapping ........................................................................................................................ 111
7.4.8. SPI2/I2S2 AF remapping ............................................................................................................... 111
7.4.9. CAN0 AF remapping ...................................................................................................................... 111
7.4.10. CAN1 AF remapping ...................................................................................................................... 111
7.4.11. CLK pins AF remapping ................................................................................................................. 112
7.5. Register definition ............................................................................................................ 113
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) ........................................................................... 113
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) ........................................................................... 115
7.5.3. Port input status register (GPIOx_ISTAT, x=A..E) ...................................................................... 116
7.5.4. Port output control register (GPIOx_OCTL, x=A..E) .................................................................. 117
7.5.5. Port bit operate register (GPIOx_BOP, x=A..E).......................................................................... 117
7.5.6. Port bit clear register (GPIOx_BC, x=A..E) ................................................................................. 118
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..E) .......................................................... 118
7.5.8. Event control register (AFIO_EC)................................................................................................. 119
7.5.9. AFIO port configuration register 0 (AFIO_PCF0) ....................................................................... 120
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0) ................................................................. 123
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1) ................................................................. 124
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2) ................................................................. 125
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3) ................................................................. 126
7.5.14. AFIO port configuration register 1 (AFIO_PCF1) ....................................................................... 127
8. CRC calculation unit (CRC) .................................................................................... 129
8.1. Overview ......................................................................................................................... 129
8.2. Characteristics .................................................................................................................. 129
8.3. Function overview ............................................................................................................ 130
8.4. Register definition ............................................................................................................ 131
8.4.1. Data register (CRC_DATA) ........................................................................................................... 131
8.4.2. Free data register (CRC_FDATA) ................................................................................................ 131
8.4.3. Control register (CRC_CTL) .......................................................................................................... 132
9. Direct memory access controller (DMA) .............................................................. 133
9.1. Overview ......................................................................................................................... 133
9.2. Characteristics .................................................................................................................. 133
9.3. Block diagram .................................................................................................................. 134
9.4. Function overview ............................................................................................................ 134
9.4.1. DMA operation................................................................................................................................. 134
9.4.2. Peripheral handshake .................................................................................................................... 136
9.4.3. Arbitration ......................................................................................................................................... 136
9.4.4. Address generation ........................................................................................................................ 137
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