GD32VF103 User Manual
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9.4.5. Circular mode .................................................................................................................................. 137
9.4.6. Memory to memory mode .............................................................................................................. 137
9.4.7. Channel configuration .................................................................................................................... 137
9.4.8. Interrupt ............................................................................................................................................ 138
9.4.9. DMA request mapping ................................................................................................................... 139
9.5. Register definition ............................................................................................................ 142
9.5.1. Interrupt flag register (DMA_INTF) ............................................................................................... 142
9.5.2. Interrupt flag clear register (DMA_INTC) .................................................................................... 143
9.5.3. Channel x control register (DMA_CHxCTL)................................................................................ 143
9.5.4. Channel x counter register (DMA_CHxCNT) .............................................................................. 145
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ........................................... 146
9.5.6. Channel x memory base address register (DMA_CHxMADDR) ............................................. 146
10. Debug (DBG) ......................................................................................................... 148
10.1. Overview ...................................................................................................................... 148
10.2. JTAG function overview................................................................................................. 148
10.2.1. Pin assignment ................................................................................................................................ 148
10.2.2. JTAG daisy chained structure ....................................................................................................... 148
10.2.3. Debug reset ..................................................................................................................................... 149
10.3. Debug hold function overview ...................................................................................... 149
10.3.1. Debug support for power saving mode ....................................................................................... 149
10.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN .................................................. 149
10.4. Register definition ........................................................................................................ 150
10.4.1. ID code register (DBG_ID) ............................................................................................................ 150
10.4.2. Control register (DBG_CTL) .......................................................................................................... 150
11. Analog-to-digital converter (ADC) ...................................................................... 153
11.1. Introduction ................................................................................................................. 153
11.2. Main features ............................................................................................................... 153
11.3. Pins and internal signals ................................................................................................ 154
11.4. Functional description .................................................................................................. 154
11.4.1. Calibration (CLB) ............................................................................................................................ 155
11.4.2. ADC clock ........................................................................................................................................ 156
11.4.3. ADCON switch ................................................................................................................................ 156
11.4.4. Regular and inserted channel groups .......................................................................................... 156
11.4.5. Conversion modes .......................................................................................................................... 156
11.4.6. Inserted channel management ..................................................................................................... 160
11.4.7. Data alignment ................................................................................................................................ 161
11.4.8. Programmable sample time .......................................................................................................... 162
11.4.9. External trigger ................................................................................................................................ 163
11.4.10. DMA request ................................................................................................................................ 163
11.4.11. Temperature sensor, and internal reference voltage V
REFINT
................................................ 163
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