GigaDevice Semiconductor GD32VF103 - Page 7

GD32VF103 User Manual
7
11.4.12. Programmable resolution (DRES) - fast conversion mode .................................................. 164
11.4.13. On-chip hardware oversampling .............................................................................................. 165
11.5. ADC sync mode ............................................................................................................. 166
11.6. Free mode .................................................................................................................... 167
11.6.1. Regular parallel mode .................................................................................................................... 168
11.6.2. Inserted parallel mode ................................................................................................................... 168
11.6.3. Follow-up fast mode ....................................................................................................................... 169
11.6.4. Follow-up slow mode ..................................................................................................................... 169
11.6.5. Trigger rotation mode ..................................................................................................................... 170
11.6.6. Combined regular parallel & inserted parallel mode ................................................................. 171
11.6.7. Combined regular parallel & trigger rotation mode .................................................................... 171
11.6.8. Combined inserted parallel & follow-up mode ............................................................................ 172
11.7. ADC interrupts .............................................................................................................. 173
11.8. ADC registers ................................................................................................................ 174
11.8.1. Status register (ADC_STAT) ......................................................................................................... 174
11.8.2. Control register 0 (ADC_CTL0) .................................................................................................... 175
11.8.3. Control register 1 (ADC_CTL1) .................................................................................................... 177
11.8.4. Sample time register 0 (ADC_SAMPT0) ..................................................................................... 179
11.8.5. Sample time register 1 (ADC_SAMPT1) ..................................................................................... 180
11.8.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) ................................................ 181
11.8.7. Watchdog high threshold register (ADC_WDHT) ...................................................................... 181
11.8.8. Watchdog low threshold register (ADC_WDLT) ......................................................................... 182
11.8.9. Regular sequence register 0 (ADC_RSQ0) ................................................................................ 182
11.8.10. Regular sequence register 1 (ADC_RSQ1) ............................................................................ 183
11.8.11. Regular sequence register 2 (ADC_RSQ2) ............................................................................ 183
11.8.12. Inserted sequence register (ADC_ISQ) .................................................................................. 184
11.8.13. Inserted data register x (ADC_IDATAx) (x= 0..3) ................................................................... 185
11.8.14. Regular data register (ADC_RDATA) ...................................................................................... 185
11.8.15. Oversample control register (ADC_OVSAMPCTL) ............................................................... 186
12. Digital-to-analog converter (DAC) ...................................................................... 188
12.1. Overview ...................................................................................................................... 188
12.2. Characteristics .............................................................................................................. 188
12.3. Function overview ........................................................................................................ 189
12.3.1. DAC enable ..................................................................................................................................... 189
12.3.2. DAC output buffer ........................................................................................................................... 190
12.3.3. DAC data configuration .................................................................................................................. 190
12.3.4. DAC trigger ...................................................................................................................................... 190
12.3.5. DAC conversion .............................................................................................................................. 190
12.3.6. DAC noise wave ............................................................................................................................. 191
12.3.7. DAC output voltage ........................................................................................................................ 192
12.3.8. DMA request .................................................................................................................................... 192