GD32VF103 User Manual
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12.3.9. DAC concurrent conversion .......................................................................................................... 192
12.4. Register definition ........................................................................................................ 193
12.4.1. Control register (DAC_CTL) .......................................................................................................... 193
12.4.2. Software trigger register (DAC_SWT) ......................................................................................... 195
12.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH) ............................................ 196
12.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ............................................... 196
12.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) ................................................ 197
12.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) ............................................ 197
12.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ............................................... 198
12.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) ................................................ 198
12.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) .............. 199
12.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ............. 199
12.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) .............. 200
12.4.12. DAC0 data output register (DAC0_DO) .................................................................................. 200
12.4.13. DAC1 data output register (DAC1_DO) .................................................................................. 201
13. Watchdog timer (WDGT) ...................................................................................... 202
13.1. Free watchdog timer (FWDGT) ...................................................................................... 202
13.1.1. Overview .......................................................................................................................................... 202
13.1.2. Characteristics................................................................................................................................. 202
13.1.3. Function overview ........................................................................................................................... 202
13.1.4. Register definition ........................................................................................................................... 205
13.2. Window watchdog timer (WWDGT) .............................................................................. 208
13.2.1. Overview .......................................................................................................................................... 208
13.2.2. Characteristics................................................................................................................................. 208
13.2.3. Function overview ........................................................................................................................... 208
13.2.4. Register definition ........................................................................................................................... 211
14. Real-time Clock (RTC) .......................................................................................... 213
14.1. Overview ...................................................................................................................... 213
14.2. Characteristics .............................................................................................................. 213
14.3. Function overview ........................................................................................................ 213
14.3.1. RTC reset ......................................................................................................................................... 214
14.3.2. RTC reading .................................................................................................................................... 214
14.3.3. RTC configuration ........................................................................................................................... 215
14.3.4. RTC flag assertion .......................................................................................................................... 215
14.4. Register definition ........................................................................................................ 217
14.4.1. RTC interrupt enable register(RTC_INTEN) ............................................................................... 217
14.4.2. RTC control register(RTC_CTL) ................................................................................................... 217
14.4.3. RTC prescaler high register (RTC_PSCH) ................................................................................. 218
14.4.4. RTC prescaler low register (RTC_PSCL) ................................................................................... 219
14.4.5. RTC divider high register (RTC_DIVH) ....................................................................................... 219
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