GD32VF103 User Manual
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Receive FIFO0 interrupt
The Receive FIFO0 interrupt can be generated by the following conditions:
Reception FIFO0 not empty: RFL0 bits in the CAN_RFIFO0 register are not ‘00’ and
RFNEIE0 in CAN_INTEN register is set.
Reception FIFO0 full: RFF0 bit in the CAN_RFIFO0 register is set and RFFIE0 in
CAN_INTEN register is set.
Reception FIFO0 overrun: RFO0 bit in the CAN_RFIFO0 register is set and RFOIE0 in
CAN_INTEN register is set.
Receive FIFO1 interrupt
The Receive FIFO1 interrupt can be generated by the following conditions:
Reception FIFO1 not empty: RFL1 bits in the CAN_RFIFO1 register are not ‘00’ and
RFNEIE1 in CAN_INTEN register is set.
Reception FIFO1 full: RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in
CAN_INTEN register is set.
Reception FIFO1 overrun: RFO1 bit in the CAN_RFIFO1 register is set and RFOIE1 in
CAN_INTEN register is set.
Error and working mode change interrupt
The error and working mode change interrupt can be generated by the following conditions:
Error: ERRIF bit in the CAN_STAT register and ERRIE bit in the CAN_INTEN register
are set. Refer to ERRIF description in the CAN_STAT register.
Wakeup: WUIF bit in the CAN_STAT register is set and WIE bit in the CAN_INTEN
register is set.
Enter sleep working mode: SLPIF bit in the CAN_STAT register is set and SLPWIE bit in
the CAN_INTEN register is set.
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