GigaDevice Semiconductor GD32VF103 - Page 81

GD32VF103 User Manual
81
16
Reserved
Must be kept at reset value
15
SPI2RST
SPI2 reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI2
14
SPI1RST
SPI1 reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI1
13:12
Reserved
Must be kept at reset value
11
WWDGTRST
WWDGT reset
This bit is set and reset by software.
0: No reset
1: Reset the WWDGT
10:6
Reserved
Must be kept at reset value
5
TIMER6RST
TIMER6 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER6
4
TIMER5RST
TIMER5 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER5
3
TIMER4RST
TIMER4 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER4
2
TIMER3RST
TIMER3 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER3
1
TIMER2RST
TIMER2 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER2
0
TIMER1RST
TIMER1 reset
This bit is set and reset by software.
0: No reset