GigaDevice Semiconductor GD32VF103 - Page 92

GD32VF103 User Manual
92
1111: (PLL2 source clock x 20)
11:8
PLL1MF[3:0]
The PLL1 clock multiplication factor
Set and reset by software.
00xx: reserve
010x: reserve
0110: (PLL1 source clock x 8)
0111: (PLL1 source clock x 9)
1000 :(PLL1 source clock x 10)
1001: (PLL1 source clock x 11)
1010: (PLL1 source clock x 12)
1011: (PLL1 source clock x 13)
1100: (PLL1 source clock x 14)
1101: (PLL1 source clock x 15)
1110 :(PLL1 source clock x 16)
1111: (PLL1 source clock x 20)
7:4
PREDV1[3:0]
PREDV1 division factor
This bit is set and reset by software. These bits can be written when PLL1 and PLL2
are disable
0000: PREDV1 input source clock not divided
0001: PREDV1 input source clock divided by 2
0010: PREDV1 input source clock divided by 3
0011: PREDV1 input source clock divided by 4
0100: PREDV1 input source clock divided by 5
0101: PREDV1 input source clock divided by 6
0110: PREDV1 input source clock divided by 7
0111: PREDV1 input source clock divided by 8
1000: PREDV1 input source clock divided by 9
1001: PREDV1 input source clock divided by 10
1010: PREDV1 input source clock divided by 11
1011: PREDV1 input source clock divided by 12
1100: PREDV1 input source clock divided by 13
1101: PREDV2 input source clock divided by 14
1110: PREDV2 input source clock divided by 15
1111: PREDV2 input source clock divided by 16
3:0
PREDV0[3:0]
PREDV0 division factor
This bit is set and reset by software. These bits can be written when PLL is disable.
Note: The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0, so modifying
Bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1.
0000: PREDV0 input source clock not divided
0001: PREDV0 input source clock divided by 2
0010: PREDV0 input source clock divided by 3
0011: PREDV0 input source clock divided by 4