GigaDevice Semiconductor GD32VF103 - Page 15

GD32VF103 User Manual
15
Figure 11-19. Trigger rotation: inserted channels in discontinuous mode ......................................... 171
Figure 11-20. Regular parallel & trigger rotation mode ........................................................................... 172
Figure 11-21. Trigger occurs during inserted conversion ...................................................................... 172
Figure 11-22 Follow-up single channel with inserted sequence CH1, CH2 ......................................... 173
Figure 12-1. DAC block diagram .................................................................................................................. 189
Figure 12-2. DAC LFSR algorithm ............................................................................................................... 191
Figure 12-3. DAC triangle noise wave ........................................................................................................ 191
Figure 13.1. Free watchdog block diagram ............................................................................................... 203
Figure 13.2. Window watchdog timer block diagram .............................................................................. 209
Figure 13.3. Window watchdog timing diagram ....................................................................................... 210
Figure 14.1. Block diagram of RTC ............................................................................................................. 214
Figure 14.2. RTC second and alarm waveform example (RTC_PSC = 3, RTC_ALRM = 2) ................ 215
Figure 14.3. RTC second and overflow waveform example (RTC_PSC= 3) ......................................... 216
Figure 15-1. Advanced timer block diagram ............................................................................................. 224
Figure 15-2. Normal mode, internal clock divided by 1 ........................................................................... 225
Figure 15-3. Counter timing diagram with prescaler division change from 1 to 2 ............................. 226
Figure 15-4. Timing chart of up counting mode, PSC=0/1 ...................................................................... 227
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................... 228
Figure 15-6. Timing chart of down counting mode, PSC=0/1 ................................................................. 229
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing ......................... 230
Figure 15-8. Timing chart of center-aligned counting mode .................................................................. 231
Figure 15-9. Repetition counter timing chart of center-aligned counting mode ................................. 232
Figure 15-10. Repetition counter timing chart of up counting mode .................................................... 232
Figure 15-11. Repetition counter timing chart of down counting mode ............................................... 233
Figure 15-12. Input capture logic ................................................................................................................. 234
Figure 15-13. Output compare logic (with complementary output, x=0,1,2) ....................................... 235
Figure 15-14. Output compare logic (CH3_O) ........................................................................................... 235
Figure 15-15. Output-compare in three modes ......................................................................................... 237
Figure 15-16. Timing chart of EAPWM ........................................................................................................ 238
Figure 15-17. Timing chart of CAPWM ....................................................................................................... 238
Figure 15-18. Complementary output with dead time insertion ............................................................. 241
Figure 15-19. Output behavior of the channel in response to a break (the break high active) ........ 242
Figure 15-20. Example of counter operation in encoder interface mode ............................................. 243
Figure 15-21. Example of encoder interface mode with CI0FE0 polarity inverted ............................. 243
Figure 15-22. Hall sensor is used to BLDC motor .................................................................................... 244
Figure 15-23. Hall sensor timing between two timers ............................................................................. 245
Figure 15-24. Restart mode .......................................................................................................................... 246
Figure 15-25. Pause mode ............................................................................................................................ 246
Figure 15-26. Event mode ............................................................................................................................. 247
Figure 15-27. Single pulse mode TIMERx_CHxCV=0x04, TIMERx_CAR=0x60.................................... 248
Figure 15-28. TIMER0 Master/Slave mode timer example ....................................................................... 248
Figure 15-29. Triggering TIMER0 with enable signal of TIMER2 ............................................................ 249
Figure 15-30. Triggering TIMER0 with update signal of TIMER2 ........................................................... 250
Figure 15-31. Pause TIMER0 with enable signal of TIMER2 ................................................................... 251