GigaDevice Semiconductor GD32VF103 - Page 16

GD32VF103 User Manual
16
Figure 15-32. Pause TIMER0 with O0CPREF signal of Timer2 ............................................................... 251
Figure 15-33. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input .............................................. 252
Figure 15-34. General Level 0 timer block diagram ................................................................................. 280
Figure 15-35. Normal mode, internal clock divided by 1 ......................................................................... 281
Figure 15-36. Counter timing diagram with prescaler division change from 1 to 2 ........................... 282
Figure 15-37. Timing chart of up counting mode, PSC=0/1 .................................................................... 283
Figure 15-38. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................. 284
Figure 15-39. Timing chart of down counting mode, PSC=0/1 ............................................................... 285
Figure 15-40. Timing chart of down counting mode, change TIMERx_CAR. ...................................... 286
Figure 15-41. Timing chart of center-aligned counting mode ................................................................ 287
Figure 15-42. Input capture logic ................................................................................................................. 288
Figure 15-43. Output-compare in three modes ......................................................................................... 290
Figure 15-44. EAPWM timechart .................................................................................................................. 291
Figure 15-45. CAPWM timechart .................................................................................................................. 291
Figure 15-46. Example of counter operation in encoder interface mode ............................................. 293
Figure 15-47. Example of encoder interface mode with CI0FE0 polarity inverted ............................. 293
Figure 15-48. Restart mode .......................................................................................................................... 294
Figure 15-49. Pause mode ............................................................................................................................ 295
Figure 15-50. Event mode ............................................................................................................................. 295
Figure 15-51. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 .................................. 296
Figure 15-52. Basic timer block diagram ................................................................................................... 318
Figure 15-53. Normal mode, internal clock divided by 1 ......................................................................... 319
Figure 15-54. Counter timing diagram with prescaler division change from 1 to 2 ........................... 320
Figure 15-55. Timing chart of up counting mode, PSC=0/1 .................................................................... 321
Figure 15-56. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................. 322
Figure 16-1. USART module block diagram .............................................................................................. 330
Figure 16-2. USART character frame (8 bits data and 1 stop bit) .......................................................... 330
Figure 16-3. USART transmit procedure .................................................................................................... 332
Figure 16-4. Receiving a frame bit by oversampling method ................................................................. 333
Figure 16-5. Configuration steps when using DMA for USART transmission ..................................... 334
Figure 16-6. Configuration steps when using DMA for USART reception ........................................... 335
Figure 16-7. Hardware flow control between two USARTs ..................................................................... 336
Figure 16-8. Hardware flow control ............................................................................................................. 336
Figure 16-9. Break frame occurs during idle state ................................................................................... 338
Figure 16-10. Break frame occurs during a frame .................................................................................... 338
Figure 16-11. Example of USART in synchronous mode ........................................................................ 339
Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) .................................................. 339
Figure 16-13. IrDA SIR ENDEC module ...................................................................................................... 340
Figure 16-14. IrDA data modulation ............................................................................................................ 340
Figure 16-15. ISO7816-3 frame format ........................................................................................................ 341
Figure 16-16. USART interrupt mapping diagram .................................................................................... 343
Figure 17-1. I2C module block diagram ..................................................................................................... 355
Figure 17-2. Data validation .......................................................................................................................... 356
Figure 17-3. START and STOP condition ................................................................................................... 356