GigaDevice Semiconductor GD32VF103 - Page 17

GD32VF103 User Manual
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Figure 17-4. Clock synchronization ............................................................................................................ 357
Figure 17-5. SDA Line arbitration ................................................................................................................ 357
Figure 17-6. I2C communication flow with 7-bit address ........................................................................ 358
Figure 17-7. I2C communication flow with 10-bit address (Master Transmit) ..................................... 358
Figure 17-8. I2C communication flow with 10-bit address (Master Receive) ...................................... 358
Figure 17-9. Programming model for slave transmitting(10-bit address mode) ................................. 360
Figure 17-10. Programming model for slave receiving(10-bit address mode) .................................... 361
Figure 17-11. Programming model for master transmitting(10-bit address mode) ............................ 363
Figure 17-12. Programming model for master receiving using Solution A(10-bit address mode) .. 365
Figure 17-13. Programming model for master receiving using solution B(10-bit address mode) .. 367
Figure 18-1. Block diagram of SPI ............................................................................................................... 381
Figure 18-2. SPI timing diagram in normal mode ..................................................................................... 382
Figure 18-3. A typical full-duplex connection ........................................................................................... 384
Figure 18-4. A typical simplex connection (Master: Receive, Slave: Transmit) .................................. 384
Figure 18-5. A typical simplex connection (Master: Transmit only, Slave: Receive) ......................... 384
Figure 18-6. A typical bidirectional connection ........................................................................................ 385
Figure 18-7. Timing diagram of TI master mode with discontinuous transfer..................................... 386
Figure 18-8. Timing diagram of TI master mode with continuous transfer .......................................... 387
Figure 18-9. Timing diagram of TI slave mode .......................................................................................... 387
Figure 18-10. Timing diagram of NSS pulse with continuous transmission ....................................... 388
Figure 18-11. Block diagram of I2S .............................................................................................................. 391
Figure 18-12. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....................... 392
Figure 18-13. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....................... 392
Figure 18-14. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)........................................... 393
Figure 18-15. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....................... 393
Figure 18-16. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ...................... 393
Figure 18-17. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ...................... 393
Figure 18-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ...................... 394
Figure 18-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ...................... 394
Figure 18-20. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ................... 394
Figure 18-21. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ................... 394
Figure 18-22. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ................... 394
Figure 18-23. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ................... 395
Figure 18-24. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ................... 395
Figure 18-25. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ................... 395
Figure 18-26. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .................. 395
Figure 18-27. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .................. 395
Figure 18-28. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ................... 396
Figure 18-29. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ................... 396
Figure 18-30. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .................... 396
Figure 18-31. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .................... 396
Figure 18-32. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ................................................................................................................................ 397
Figure 18-33. PCM standard short frame synchronization mode timing diagram (DTLEN=00,