GigaDevice Semiconductor GD32VF103 - Page 18

GD32VF103 User Manual
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CHLEN=0, CKPL=1) ................................................................................................................................ 397
Figure 18-34. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ................................................................................................................................ 397
Figure 18-35. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ................................................................................................................................ 397
Figure 18-36. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ................................................................................................................................ 397
Figure 18-37. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ................................................................................................................................ 397
Figure 18-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ................................................................................................................................ 398
Figure 18-39. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ................................................................................................................................ 398
Figure 18-40. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ................................................................................................................................ 398
Figure 18-41. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ................................................................................................................................ 398
Figure 18-42. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ................................................................................................................................ 398
Figure 18-43. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-44. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ................................................................................................................................ 399
Figure 18-45. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-46. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ................................................................................................................................ 399
Figure 18-47. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-48. Block diagram of I2S clock generator ................................................................................ 400
Figure 19-1. The EXMC block diagram ....................................................................................................... 417
Figure 19-2. EXMC memory banks .............................................................................................................. 418
Figure 19-3. Region of bank0 address mapping ....................................................................................... 418
Figure 19-4. Multiplex mode read access .................................................................................................. 421
Figure 19-5. Multiplex mode write access ................................................................................................. 421
Figure 19-6. Read access timing diagram under async-wait signal assertion.................................... 423
Figure 19-7. Write access timing diagram under async-wait signal assertion ................................... 423
Figure 20-1. CAN module block diagram ................................................................................................... 428
Figure 20-2. Transmission register ............................................................................................................. 430
Figure 20-3. State of transmission mailbox ............................................................................................... 431
Figure 20-4. Reception register ................................................................................................................... 432
Figure 20-5. 32-bit filter ................................................................................................................................. 434
Figure 20-6. 16-bit filter ................................................................................................................................. 434
Figure 20-7. 32-bit mask mode filter ........................................................................................................... 434