GigaDevice Semiconductor GD32VF103 - Page 446

GD32VF103 User Manual
446
This bit is set by hardware while the transmit error is occurred. This bit reset by
software when write 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit reset
by hardware when next transmit start.
10
MAL1
Mailbox 1 arbitration lost
This bit is set while the arbitration lost is occurred. This bit reset by software when
write 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit reset by hardware
when next transmit start.
9
MTFNERR1
Mailbox 1 transmit finished and no error
This bit is set when the transmission finished and no error. This bit reset by
software when write 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit reset
by hardware when the transmission finished with error.
0: Mailbox 1 transmit finished with error
1: Mailbox 1 transmit finished and no error
8
MTF1
Mailbox 1 transmit finished
This bit is set by hardware when the transmission finish or abort. This bit reset by
software when write 1 to this bit or TEN bit in CAN_TMI1 is 1.
0: Mailbox 1 transmit is progressing
1: Mailbox 1 transmit finished
7
MST0
Mailbox 0 stop transmitting
This bit is set by the software to stop mailbox 0 transmitting.
This bit is reset by the hardware while the mailbox 0 is empty.
6:4
Reserved
Must be kept at reset value
3
MTE0
Mailbox 0 transmit error
This bit is set by hardware while the transmit error is occurred. This bit reset by
software when write 1 to this bit or MTF0 bit in CAN_TSTAT register. This bit reset
by hardware when next transmit start.
2
MAL0
Mailbox 0 arbitration lost
This bit is set while the arbitration lost is occurred. This bit reset by software when
write 1 to this bit or MTF0 bit in CAN_TSTAT register. This bit reset by hardware
when next transmit start.
1
MTFNERR0
Mailbox 0 transmit finished and no error
This bit is set when the transmission finished and no error. This bit reset by
software when write 1 to this bit or MTF0 bit in CAN_TSTAT register. This bit reset
by hardware when the transmission finished with error.
0: Mailbox 0 transmit finished with error
1: Mailbox 0 transmit finished and no error
0
MTF0
Mailbox 0 transmit finished
This bit is set by hardware when the transmission finish or abort. This bit reset by
software when write 1 to this bit or TEN bit in CAN_TMI0 is 1.