GD32VF103 User Manual
445
0: Transmit mailbox 1 not empty
1: Transmit mailbox 1 empty
0: Transmit mailbox 0 not empty
1: Transmit mailbox 0 empty
These bits are the number of the transmit FIFO mailbox in which the frame will be
transmitted if at least one mailbox is empty.
These bits are the number of the transmit FIFO mailbox in which the frame will be
transmitted lastly if all mailboxes are full.
Mailbox 2 stop transmitting
This bit is set by the software to stop mailbox 2 transmitting.
This bit is reset by the hardware while the mailbox 2 is empty.
Must be kept at reset value
This bit is set by hardware while the transmit error is occurred. This bit reset by
software when write 1 to this bit or MTF2 bit in CAN_TSTAT register. This bit reset
by hardware when next transmit start.
Mailbox 2 arbitration lost
This bit is set while the arbitration lost is occurred. This bit reset by software when
write 1 to this bit or MTF2 bit in CAN_TSTAT register. This bit reset by hardware
when next transmit start.
Mailbox 2 transmit finished and no error
This bit is set when the transmission finished and no error. This bit reset by
software when write 1 to this bit or MTF2 bit in CAN_TSTAT register. This bit reset
by hardware when the transmission finished with error.
0: Mailbox 2 transmit finished with error
1: Mailbox 2 transmit finished and no error
Mailbox 2 transmit finished
This bit set by hardware when the transmission finish or abort. This bit reset by
software when write 1 to this bit or TEN bit in CAN_TMI2 is 1.
0: Mailbox 2 transmit is progressing
1: Mailbox 2 transmit finished
Mailbox 1 stop transmitting
This bit is set by the software to stop mailbox 1 transmitting.
This bit is reset by the hardware while the mailbox 1 is empty.
Must be kept at reset value
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