GigaDevice Semiconductor GD32VF103 - Page 499

GD32VF103 User Manual
499
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1:0
CLKSEL[1:0]
Clock select for usbclock.
01: 48MHz clock
others: reserved
Host frame interval register (USBFS_HFT)
Address offset: 0x0404
Reset value: 0x0000 BB80
This register sets the frame interval for the current enumerating speed when USBFS controller
is enumerating.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FRI[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
FRI[15:0]
Frame interval
This value describes the frame time in terms of PHY clocks. Each time when port is
enabled after a port reset operation, USBFS use a proper value according to the
current speed, and software can write to this field to change the value. This value
should be calculated using the frequency described below:
Full-Speed: 48MHz
Low-Speed: 6MHz
Host frame information remaining register (USBFS_HFINFR)
Address offset: 0x408
Reset value: 0xBB80 0000
This register has to be accessed by word (32-bit)