GigaDevice Semiconductor GD32VF103 - Page 84

GD32VF103 User Manual
84
11
TIMER0EN
TIMER0 clock enable
This bit is set and reset by software.
0: Disabled TIMER0 clock
1: Enabled TIMER0 clock
10
ADC1EN
ADC1 clock enable
This bit is set and reset by software.
0: Disabled ADC1 clock
1: Enabled ADC1 clock
9
ADC0EN
ADC0 clock enable
This bit is set and reset by software.
0: Disabled ADC0 clock
1: Enabled ADC0 clock
8:7
Reserved
Must be kept at reset value
6
PEEN
GPIO port E clock enable
This bit is set and reset by software.
0: Disabled GPIO port E clock
1: Enabled GPIO port E clock
5
PDEN
GPIO port D clock enable
This bit is set and reset by software.
0: Disabled GPIO port D clock
1: Enabled GPIO port D clock
4
PCEN
GPIO port C clock enable
This bit is set and reset by software.
0: Disabled GPIO port C clock
1: Enabled GPIO port C clock
3
PBEN
GPIO port B clock enable
This bit is set and reset by software.
0: Disabled GPIO port B clock
1: Enabled GPIO port B clock
2
PAEN
GPIO port A clock enable
This bit is set and reset by software.
0: Disabled GPIO port A clock
1: Enabled GPIO port A clock
1
Reserved
Must be kept at reset value
0
AFEN
Alternate function IO clock enable
This bit is set and reset by software.
0: Disabled Alternate Function IO clock
1: Enabled Alternate Function IO clock