GigaDevice Semiconductor GD32VF103 - Page 73

GD32VF103 User Manual
73
11100: (PLL source clock x 29)
11101: (PLL source clock x 30)
11110: (PLL source clock x 31)
11111: (PLL source clock x 32)
17
PREDV0_LSB
The LSB of PREDV0 division factor
This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1. Changing
the PREDV0 division factor bit [0] from RCU_CFG1, this bit is also changed. When
the PREDV0 division factor bits [3:1] are not set, this bit controls PREDV0 input
clock divided by 2 or not.
16
PLLSEL
PLL Clock Source Selection
Set and reset by software to control the PLL clock source.
0: (IRC8M / 2) clock selected as source clock of PLL
1: HXTAL selected as source clock of PLL
15:14
ADCPSC[1:0]
ADC clock prescaler selection
These bits and bit 28 of RCU_CFG0 are written by software to define the ADC
prescaler factor.Set and cleared by software.
000: (CK_APB2 / 2) selected
001: (CK_APB2 / 4) selected
010: (CK_APB2 / 6) selected
011: (CK_APB2 / 8) selected
100: (CK_APB2 / 2) selected
101: (CK_APB2 / 12) selected
110: (CK_APB2 / 8) selected
111: (CK_APB2 / 16) selected
13:11
APB2PSC[2:0]
APB2 prescaler selection
Set and reset by software to control the APB2 clock division ratio.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
10:8
APB1PSC[2:0]
APB1 prescaler selection
Set and reset by software to control the APB1 clock division ratio.
Caution: The CK_APB1 output frequency must not exceed 60 MHz.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
7:4
AHBPSC[3:0]
AHB prescaler selection
Set and reset by software to control the AHB clock division ratio