GigaDevice Semiconductor GD32VF103 - Page 348

GD32VF103 User Manual
348
0: Even parity
1: Odd parity
8
PERRIE
Parity error interrupt enable
If this bit is set, an interrupt occurs when the PERR bit in USART_STAT is set.
0: Parity error interrupt is disabled
1: Parity error interrupt is enabled
7
TBEIE
Transmitter buffer empty interrupt enable
If this bit is set, an interrupt occurs when the TBE bit in USART_STAT is set.
0: Transmitter buffer empty interrupt is disabled
1: Transmitter buffer empty interrupt is enabled
6
TCIE
Transmission complete interrupt enable
If this bit is set, an interrupt occurs when the TC bit in USART_STAT is set.
0: Transmission complete interrupt is disabled
1: Transmission complete interrupt is enabled
5
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
If this bit is set, an interrupt occurs when the RBNE bit or the ORERR bit in
USART_STAT is set.
0: Read data register not empty interrupt and overrun error interrupt disabled
1: Read data register not empty interrupt and overrun error interrupt enabled
4
IDLEIE
IDLE line detected interrupt enable
If this bit is set, an interrupt occurs when the IDLEF bit in USART_STAT is set.
0: IDLE line detected interrupt disabled
1: IDLE line detected interrupt enabled
3
TEN
Transmitter enable
0: Transmitter is disabled
1: Transmitter is enabled
2
REN
Receiver enable
0: Receiver is disabled
1: Receiver is enabled
1
RWU
Receiver wakes up from mute mode.
Software can set this bit to make the USART work in mute mode and clear this bit
to wake up the USART.
If it is configured to wake up by idle frame (WM=0), this bit can be cleared by
hardware when an idle frame has been detected. If it is configured to wake up by
address matching (WM=1), this bit can be cleared by hardware when receiving an
address match frame or set by hardware when receiving an address mismatch
frame.
0: Receiver in active mode
1: Receiver in mute mode