GD32VF103 User Manual
36
Unlock the FMC_CTL registers if necessary.
Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
Set the PG bit in FMC_CTL registers.
Write a 32-bit word/16-bit half word to desired absolute address (0x08XX XXXX) by
DBUS.
Wait until all the operations have been finished by checking the value of the BUSY bit in
FMC_STAT registers.
Read and verify the Flash memory if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and
an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. Note
that the word/half word programming operation checks the address if it has been erased. If
the address has not been erased, PGERR bit in the FMC_STAT registers will be set when
programming the address except 0x0. Note that the PG bit must be set before the word/half
word programming operation. Additionally, the program operation will be ignored on
erase/program protected pages and WPERR bit in FMC_STAT is set. In these conditions, a
flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTL
registers is set. The software can check the PGERR bit or WPERR bit in the FMC_STAT
registers to detect which condition occurred in the interrupt handler. Figure 2-3. Process of
word program operation displays the word programming operation flow.
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