GD32VF103 User Manual
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18.4. SPI signal description .................................................................................................... 381
18.4.1. Normal configuration ...................................................................................................................... 381
18.5. SPI function overview ................................................................................................... 382
18.5.1. SPI clock timing and data format .................................................................................................. 382
18.5.2. NSS function .................................................................................................................................... 382
18.5.3. SPI operating modes ...................................................................................................................... 383
18.5.4. DMA function ................................................................................................................................... 389
18.5.5. CRC function ................................................................................................................................... 389
18.6. SPI interrupts ............................................................................................................... 389
18.6.1. Status flags ...................................................................................................................................... 389
18.6.2. Error flags ........................................................................................................................................ 390
18.7. I2S block diagram ......................................................................................................... 391
18.8. I2S signal description .................................................................................................... 391
18.9. I2S function overview ................................................................................................... 392
18.9.1. I2S audio standards ....................................................................................................................... 392
18.9.2. I2S clock ........................................................................................................................................... 400
18.9.3. Operation ......................................................................................................................................... 401
18.9.4. DMA function ................................................................................................................................... 403
18.10. I2S interrupts................................................................................................................ 404
18.10.1. Status flags .................................................................................................................................. 404
18.10.2. Error flags .................................................................................................................................... 404
18.11. Register definition ........................................................................................................ 406
18.11.1. Control register 0 (SPI_CTL0) .................................................................................................. 406
18.11.2. Control register 1 (SPI_CTL1) .................................................................................................. 408
18.11.3. Status register (SPI_STAT) ....................................................................................................... 409
18.11.4. Data register (SPI_DATA).......................................................................................................... 410
18.11.5. CRC polynomial register (SPI_CRCPOLY) ............................................................................ 411
18.11.6. RX CRC register (SPI_RCRC) ................................................................................................. 411
18.11.7. TX CRC register (SPI_TCRC) .................................................................................................. 412
18.11.8. I2S control register (SPI_I2SCTL) ........................................................................................... 413
18.11.9. I2S clock prescaler register (SPI_I2SPSC) ............................................................................ 414
19. External memory controller (EXMC) .................................................................. 416
19.1. Overview .................................................................................................................... 416
19.2. Characteristics .......................................................................................................... 416
19.3. Function overview .................................................................................................... 416
19.3.1. Block diagram .................................................................................................................................. 416
19.3.2. Basic regulation of EXMC access ................................................................................................ 417
19.3.3. External device address mapping ................................................................................................ 418
19.3.4. NOR/PSRAM controller ................................................................................................................. 418
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