GD32VF103 User Manual
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19.4. Register definition .................................................................................................... 424
19.4.1. NOR/PSRAM controller registers ................................................................................................. 424
20. Controller area network (CAN) ........................................................................... 427
20.1. Overview .................................................................................................................... 427
20.2. Characteristics .......................................................................................................... 427
20.3. Function overview .................................................................................................... 428
20.3.1. Working mode ................................................................................................................................. 428
20.3.2. Communication modes .................................................................................................................. 429
20.3.3. Data transmission ........................................................................................................................... 430
20.3.4. Data reception ................................................................................................................................. 432
20.3.5. Filtering function .............................................................................................................................. 433
20.3.6. Time-triggered communication ..................................................................................................... 436
20.3.7. Communication parameters .......................................................................................................... 437
20.3.8. Error flags ........................................................................................................................................ 438
20.3.9. CAN interrupts ................................................................................................................................. 439
20.4. Register definition .................................................................................................... 441
20.4.1. Control register (CAN_CTL) .......................................................................................................... 441
20.4.2. Status register (CAN_STAT) ......................................................................................................... 442
20.4.3. Transmit status register (CAN_TSTAT) ....................................................................................... 444
20.4.4. Receive message FIFO0 register (CAN_RFIFO0) .................................................................... 447
20.4.5. Receive message FIFO1 register (CAN_RFIFO1) .................................................................... 447
20.4.6. Interrupt enable register (CAN_INTEN) ...................................................................................... 448
20.4.7. Error register (CAN_ERR) ............................................................................................................. 450
20.4.8. Bit timing register (CAN_BT) ......................................................................................................... 451
20.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ........................................................ 452
20.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) ................................................... 453
20.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) .............................................. 453
20.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) .............................................. 454
20.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) ................................... 454
20.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) .................................. 455
20.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) ............................. 456
20.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ............................. 456
20.4.17. Filter control register (CAN_FCTL) .......................................................................................... 457
20.4.18. Filter mode configuration register (CAN_FMCFG) ................................................................ 457
20.4.19. Filter scale configuration register (CAN_FSCFG) ................................................................. 458
20.4.20. Filter associated FIFO register (CAN_FAFIFO) ..................................................................... 458
20.4.21. Filter working register (CAN_FW) ............................................................................................ 459
20.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) ..................................................... 459
21. Universal serial bus full-speed interface (USBFS) .......................................... 461
21.1. Overview ...................................................................................................................... 461
21.2. Characteristics .............................................................................................................. 461
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