GigaDevice Semiconductor GD32VF103 - Page 151

GD32VF103 User Manual
151
1: the receive register of CAN1 stops receiving data when core halted
20
TIMER6_HOLD
TIMER 6 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 6 counter for debug when core halted
19
TIMER5_HOLD
TIMER 5 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 5 counter for debug when core halted
18
TIMER4_HOLD
TIMER 4 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 4 counter for debug when core halted
17
Reserved
Must be kept at reset value
16
I2C1_HOLD
I2C1 hold bit
This bit is set and reset by software
0: no effect
1: hold the I2C1 SMBUS timeout for debug when core halted
15
I2C0_HOLD
I2C0 hold bit
This bit is set and reset by software
0: no effect
1: hold the I2C0 SMBUS timeout for debug when core halted
14
CAN0_HOLD
CAN0 hold bit
This bit is set and reset by software
0: no effect
1: the receive register of CAN0 stops receiving data when core halted
13
TIMER3_HOLD
TIMER 3 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 3 counter for debug when core halted
12
TIMER2_HOLD
TIMER 2 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 2 counter for debug when core halted
11
TIMER1_HOLD
TIMER 1 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 1 counter for debug when core halted