GigaDevice Semiconductor GD32VF103 - Page 152

GD32VF103 User Manual
152
10
TIMER0_HOLD
TIMER 0 hold bit
This bit is set and reset by software
0: no effect
1: hold the TIMER 0 counter for debug when core halted
9
WWDGT_HOLD
WWDGT hold bit
This bit is set and reset by software
0: no effect
1: hold the WWDGT counter clock for debug when core halted
8
FWDGT_HOLD
FWDGT hold bit
This bit is set and reset by software
0: no effect
1: hold the FWDGT counter clock for debug when core halted
7:3
Reserved
Must be kept at reset value
2
STB_HOLD
Standby mode hold register
This bit is set and reset by software
0: no effect
1: At the standby mode, the clock of AHB bus and system clock are provided by
CK_IRC8M, a system reset generated when exit standby mode
1
DSLP_HOLD
Deep-sleep mode hold register
This bit is set and reset by software
0: no effect
1: At the Deep-sleep mode, the clock of AHB bus and system clock are provided by
CK_IRC8M
0
SLP_HOLD
Sleep mode hold register
This bit is set and reset by software
0: no effect
1: At the sleep mode, the clock of AHB is on.