Anritsu MS9740A - Status Byte Register

Chapter 2 Before Use
2-20
2.6.2 Status Byte Register
The meaning of each bit of the status byte register is shown in the
following table.
Table 2.6.2-1 Meaning of Status Byte Register
Bit Explanation
7
Not used; always 0
6
MSS (Master Summary Register)
It is the logical sum of the bit 5 to 0, bit 7 logical
product of the status byte register and the service
request enable register.
5
This is the logical sum of each bit of the logical product
of the standard event status register and standard
event enable register.
4
MAV (Message Available summary)
This is always 1 when there is a response message in
the output queue of this instrument
3
This is the logical sum of each bit of the logical product
of the error event register and event enable register.
2
This is the logical sum of each bit of the logical product
of the end event register and event enable register.
1
Not used; always 0
0
Not used; always 0
The following methods are used to read the status byte register.
•
Using common
*STB?
command
•
Using GPIB serial poll (when Option 001 installed)
Read the GPIB interface manual for the serial poll method.
When using serial polling, even if bit 6 is 1, it becomes 0 after reading
once.
The *SRE and *SRE? common commands can be used for setting and
reading the service request enable register for setting reading of the
status byte register. To output the status byte register data, set the bit
corresponding to the service request enable register to 1.
Bits 5, 3, and 2 of the status byte register can be set to 0 using the
*CLS
common command.
When
*CLS
is sent after a command or when a query is sent after
*CLS
,
the send queue is cleared and bit 4 is set to 0.