Anritsu MS9740A - Event Register

2.6 Checking Instrument Status
2-21
2
Before Use
2.6.3 Event Register
Standard Event Status Register
The meaning of each bit of the standard event status register is listed in
the table below.
Table 2.6.3-1 Meaning of Standard Event Status Register
Bit Explanation
7
Power-on
Becomes 1 at power-on and returns 0 when read.
6
Not used; always 0
5
Command Error
Becomes 1 when received undefined program message,
message that cannot executed according to syntax, or
message with spelling error
4
Execution Error
Becomes 1 when received program message that cannot
be executed.
3
Device Dependent Error
Becomes 1 at errors other than command, execution
and query errors.
2
Query Error
Becomes 1 when no data to read in output queue or
output queue data fails for some reason.
1
Not used; always 0
0
Operation Complete
Becomes 1 when all command operation completed
after the *OPC command operation.
Bit 7 to bit 0 of the standard event register can be read by the
*ESR?
command. The standard event register returns to 0 when read.
The standard event register enable register can be set and read using the
*ESE
and
*ESE?
commands. To output standard event register data, set
the bit corresponding to the enable register to 1.
The standard event register can be set to 0 using the
*CLS
command.